A ADM7171ACPZ-1.8 circuit is set to provide DRVDD power supply for AD9650 AD converter module. And the data coming out of the AD9650 is transferred to a XIlinx FPGA core.Before the FPGA core is connected to the AD module, the output of ADM7171A keeps…
The AD9650 Evaluation PCB Gerbers are avail from the "Evaluation Documentation" Link on the AD9650 Product Page at http://www.analog.com/en/search.html?q=AD9650
Operation of the AD9650 Eval Brd is detailed in UG-003 avail from the…
I have the question about the AD9650.
I will use the SPI to configuration for AD9650.
I think that the AD9650 starts in the mode of without the SPI after the power-up.
After the power-up of the AD9650, is waiting time necessary between until…
I have a question about the VCM pin of the AD9650.
I am using the AD9650 by the configuration like Figure 79 in the AD9650 datasheet.
In my circuit, the VCM of AD9650 operates abnormally.
AS for the operation, the VCM does a continuous toggle…
I use AD9650 in my design, it is 105MHz, now I can read reg #001, I can also read and write other reg.
But I can not write reg #00B, any value write to it when read is 0x00, I can make sure my work on SPI is OK, Why?
when i look at the datasheet of ad9650 i understand that if we want to use lvds mode we should configure the device through its SPI. Is there any other method, if there is not, do you know if there is a ready VHDL module in order to configure ad9650 through…
Hi, I am wondering what is the current limit on the AIN inputs for the AD9650,
I am designing a high speed sampling system that has a +-10V peak pulse so I need dc coupled inputs.
I'm using the ADA4350 to drive the AD9650. The front-end circuit of AD9650 is shown below. The sample rate is 20MHz.
When I input a 100KHz sine wave to the ADA4350, The sample data is a stepped sine waves when ploted.
I have another PCB of AD9650…
When I input a 100KHz sine wave to the ADA4350, The sample data is a stepped sine waves when ploted. I have another PCB of AD9650…