I have been programming AD9522 at input frequency 10 MHz and required output frequency 100 MHz. As I am probing Lock Detect (LD) pin, I am getting glitches of about 250 ns at random intervals.
In another case, I am programming AD9522 at input freq…
In the evaluation board for AD9522, separate power supplies are used for Vs and Vcp.
Is it mandatory?
Can I power both the supplies from a single LDO - ADP3339.
Hi, appreciate your help first
There are high speed AD, DA, FPGA, DSP and two Clock generation chip AD9522 on the board, one for AD and DA, one for FPGA MGT and DSP.
The AD9522 schematics are attached as fpga.pdf, and the value of resistors and caps…
John, This is a datasheet error. Thanks for pointing it out. This errant figure was located in a few of our older datasheets. If you want to see the correct figure, please check the AD9522 datasheet.
I would like to confirm about unused CLK/CLK# input pin of AD9522-1.
What is the recommended state? (Open, Pul-up,,,)
Just to note. If you like the AD9516, but require power-on start up. The AD9520 and AD9522 are similar to the AD9516, but are available with an integrated EEPROM which may be programmed to configure the device on power up.
AD9522-4: Does high-low-high pulse at reset pin (pin 23) after power-up is needed to be done externally or it is done internally by the chip itself?
in my design an AD9522-4 is involved in order to generate all the clocks required in the system from a 100MHz reference.
The on-chip VCO is tuned to 1600MHz in order to generate all the frequencies I require. Among them, an 800MHz single…