Thank you for your interest in AD9269.
I emailed you sample Verilog FPGA capture code for AD9269 that was written for Xilinx Virtex4. This code was written for the HSC-ADC-EVALCZ FPGA board that connects to the AD9269 evaluation board through…
The FPGA we use to capture AD9269 outputs is the Xilinx Virtex4 (on HSC-ADC-EVALCZ). Sample FPGA code for AD9269 data capture can be found here . This is provided:
Flowing picture is the AD9258 and AD9269 footprint data, as discribed in the datasheet, AD9258 and AD9269 is pin compatible.But, the blue circle sign in the picture, the data may be wrong？Thanks！
I am looking for an ADC like AD9269 but with better resolution with a sampling rate of 30 Mhz or more.
Application is sampling a CCD sensor.
Is there solution or something planned in near term ?
If you go to the AD9269 product page ( http://www.analog.com/en/products/analog-to-digital-converters/ad9269.html ) and scroll down to the "Tools & Simulations" section there is a link called "AD9269LFCSP/AD9266LFCSP S Parameter". Double…
We use AD9269 on our project.
For ADC CLK jitter, we just see the curve at Figure 55 in data-sheet P.24. as below,
and does not see any specification about it.
We plan use 13MHz or 52MHz CLK source input to AD9269 (CLK spec. as below)…
The AD9269 evaluation board comes with the ADL5562 amplifier, but the components around the amplifier (resistors and capacitors) at the inputs, outputs and power supply lines are not installed. These uninstalled…
Thanks for your question. As you have observed, the as-designed default output timing of the AD9269 in interleaved output mode has DCO and data switching at the same time. Very often the receiving device is an FPGA, which can be programmed…
How valid Duty Cycle range for input clock AD9269?