Hi, I have question about ad9523's 72th pin.
I'm using VCXO which center frequency is 125MHz.
The problem is that when I tried to do get a signal on pin Pll1_out, the signal doesn't come out anything. It's just look like ground.
I powered up the PLL1 and divider was just 1.0, and I used ad9523 evaluation software to match the register.( I used the FPGA to wirte SPI, this worked well. I verify it with SDO pin.)
The reason I am guessing is that my AD9523 doesn't read the VCXO's signal. So is there any way or spi register that I have to modify? or do I need to give signal to other pin?
sorry for short English.
I'm sorry for the delay in getting back to you.
to get the VCXO output at pin PLL1OUT, you need to enable the PLL1 output driver by setting bit 7 in register 0x1BB to 1. The best way is to use an evaluation board, obtain a configuration file from it based on your choices, and see the registers setup from this file.