I configure the ad9528,PLL1 have locked,but PLL2 can not lock.can you supply a correct .stp file.thanks!
Ref A = 250MHz, VCXO = 100MHz, SysRef = 250MHz,
in the future, please post questions related to the clocking chips like the AD9528 in the Clock and Timing section of Engineer Zone.
I propose the following debug method:
In this way, the VCXO becomes the reference of PLL2 at his nominal frequency. Then, after loading the chip with these new settings, please click on VCO Calibrate
Then you should click on SYNC button in the tools to provide the PLL2 output at the output distribution registers.
Please click on Status button and send me a picture of it:
I don't have tools to configure the AD9528. I use FPGA to configure 9528 through SPI interface.
I need three clock (1)1GHz (2)250MHz (3)125MHz. But VCO = 4GHz can not lock.
Now,VCO <= 3.6GHz can lock. I can only get 3.6G/4 = 900MHz or 3.6G/3 = 1.2GHz.
Doesn't this chip support VCO equal to 4G?
can you supply a correct .stp file.
You should use the AD9528 tools to get the register value that you will then use in the FPGA to initialize the AD9528. Based on the photos you attached, I created a stp file that I attach2625.AD9528_setup_20190418.zip
I have the following comments on your settings:
If REFB is disabled, it does not matter the Ref Select pin can override Switchover.
Why did you change the Loop Filter settings in the PLL2 controls menu? The AD9528 website gives you a startup stp file that has certain settings of the loop filter. Why not using these?
The VCO of PLL2 supports 4.0GHz.
Still unable to lock.I tried the default Loop Filter settings,but can not lock.This is the STP I configured.
The project is in a hurry. I need a STP file that confirms lock.
The AD9528 evaluation board has a 122.88 MHz VCXO, so this makes it challenging to replicate exactly your setup. However, I propose for your case the following:
- close the PLL1 loop using the PLL2 feedback
- change the PLL1 filter to the capacitors and resistors from the eval board.
With these changes in mind, I created a setup for my evaluation board that I got to work with a PLL2 VCO equal to 3.93 GHz, generating 983.04 MHz at OUT0.
I then replicated that setup to your case and I created a setup file as well. I attach both setups.
Please look at them with the evaluation software.