AD9162 DAC Clocking solution above 4.5GHz using LTC6952.


I am looking to use an AD9162 high speed DAC.

In order to generate the system clocking architecture we are looking to use an LTC6952.

It is understood how we can achieve deterministic latency in the JESD204 link if the DAC clock is less than the 4.5GHZ capability of the LTC6952.

If however we were wanting to run the DAC clock higher than this it looks like from the LTC6952 datasheet that this can be achieved by using an LTC6955-1 to drive the DAC clock.
The div2 output of the LTC6955-1 could then drive the LTC6952 which would then generate the other system clocks/Sysrefs to achieve deterministic latency in the JESD link.

Can we be confident that this will be a stable solution over all temperature ranges and between devices ? It would appear that adjusting the ADEL values can compensate for temperature changes.

I am wondering if another solution would be to use an LTC6952 followed by an ADF4731. The LTC6952 will generate the reference and Sysref and with the ADF4371 set for integer mode  we could  use the fundamental range of the VCOs which is in the 4-8Ghz band as the low jitter DAC clock (approx. 45-57fs rms).

Of the above possible solutions is there a more recognised solution that Analog Devices would recommend or indeed anothter solution entirely?

Thank you for any help in this regard.