I am looking to use an AD9162 high speed DAC.
In order to generate the system clocking architecture we are looking to use an LTC6952.
It is understood how we can achieve deterministic latency in the JESD204 link if the DAC clock is less than the 4.5GHZ capability of the LTC6952.
If however we were wanting to run the DAC clock higher than this it looks like from the LTC6952 datasheet that this can be achieved by using an LTC6955-1 to drive the DAC clock.The div2 output of the LTC6955-1 could then drive the LTC6952 which would then generate the other system clocks/Sysrefs to achieve deterministic latency in the JESD link.
Can we be confident that this will be a stable solution over all temperature ranges and between devices ? It would appear that adjusting the ADEL values can compensate for temperature changes.
I am wondering if another solution would be to use an LTC6952 followed by an ADF4731. The LTC6952 will generate the reference and Sysref and with the ADF4371 set for integer mode we could use the fundamental range of the VCOs which is in the 4-8Ghz band as the low jitter DAC clock (approx. 45-57fs rms).
Of the above possible solutions is there a more recognised solution that Analog Devices would recommend or indeed anothter solution entirely?
Thank you for any help in this regard.
You have touched on two of our preferred approaches. If your clocks are less then 6GHz you can also use the HMC987 and HMC7044, similar to the LTC6955-1 and LTC6952 method. The main difference is the location of the divide by 2 on the HMC7044 input (rather than the HMC987, like the LTC6955-1)
Which ever method you pick you will need to adjust for the temperature drift to stay single cycle clock accurate. The ADF4371, like most PLL/VCO's, has some reference input to rf output drift over temperature. This is not commonly spec'd for these type of parts.
The big advantage of using a buffer (HMC987 or LTC6955-1) is the significant power savings for multiple clocks at a given performance node. This method allows for timing adjustments on SYSREF over temperature. This method is limited to 7.5 GHz.
The nice feature of using a LTC6952 to create reference signals to the ADF4371 and SYSREF signals, is the ADEL can be used to adjust reference and SYSREF edges. This gives you phase control of the ADF4371 clock output also (the clock output should track the reference edge). This method is probably used more often as it gives us the capability to clock up to 16 GHz. For whatever, reason it seems like most customer's are asking for clock solutions <=3 GHz, or >9 GHz.
I can work with you on this. It would probably be helpful for me to know some of your high level system architecture desires. Number of DAC clocks, and desired max DAC clock frequency? If you have some ADCs, feel free to forward on that information also.
Thanks for replying, I was away on holiday for a bit and was working on other things but am back on this subject again.
I am in the process of ordering in an Eval board for the LTC6955-1 so was wondering if I could use this with the HMC7044 instead of theHMC987 for operation upto 6GHz. So would use the divide by 2 output of the LTC6955-1 rather than the divide by 2 input on PLL2 of the HMC7044. I already have the eval card for the HMC7044.
I am afraid that I cannot disclose what specific frequencies that we are wanting to operate at.
Thanks again for any help.
Moved to the"Clock and Timing" community ChrisPearson
Del, Thanks for moving this to the clock and timing community. For some reason I was not notified about this reply from a month ago.
You can do that. But if possible I would use the LTC6955(or HMC987) and the HMC7044 /2 input as this would avoid a small /2 spur on the LTC6955-1 /1 outputs.
Thanks for that will try that out once the LTC6955-1 comes in.